1. Field of the Invention
The present invention relates to electrical signal processing, and, in particular, to circuitry that provides a variable-gain amplifier (VGA) function and/or a continuous-time filter (CTF) function.
2. Description of the Related Art
FIG. 1 shows a schematic circuit diagram of a prior-art MOSFET open-loop variable-gain amplifier (VGA) 100. VGA 100 has two equivalent, differential transistor pairs M6, M7 and M8, M9 connected, on the drain side, to two equivalent transconductance load devices M4 and M5 and, on the source side, to two current sinks 102 and 104. The differential input signal VIP, VIN is applied to the gates of the differential transistor pairs, while the differential output signal VOP, VON is presented at the drains of the differential transistor pairs. In particular, VIP is applied to the gates of M6 and M9, VIN is applied to the gates of M7 and M8, VOP is presented at a node shared by the drains of M7 and M9, and VON is presented at a node shared by the drains of M6 and M8.
Each transconductance load device is a MOSFET whose source is connected to the drain of one of the transistors in each differential pair and whose source and gate are both connected to reference voltage VDD. In particular, the source of M4 is connected to the drains of M6 and M8, while the source of M5 is connected to the drains of M7 and M9.
Each current sink is connected between the sources of both transistors in one of the differential pairs and reference voltage VSS (e.g., ground). In particular, current sink 102 is connected to a node shared by the sources of M6 and M7, while current sink 104 is connected to a node shared by the sources of M8 and M9. The current through current sink 104 is Ineg, while the current through current sink 102 is Itotal-Ineg.
To achieve log-linear gain adjustment using VGA 100, the current Ineg is adjusted in a linear fashion (keeping Itotal constant), providing near exponential gain control. A single pole ωp at the output nodes is given by Equation (1) as follows:
                              ω          p                =                              g            mload                                C            l                                              (        1        )            where gmload is the output transconductance due to the load devices, and C1 is the sum of all parasitic capacitances at the output node VON.
As indicated by Equation (1), the bandwidth of VGA 100 is limited by the output transconductance and load capacitance. In addition, common-mode and power-supply rejection are limited by the direct connection of the gain terminals of transconductors M4 and M5 to the power supply or voltage reference VDD.